1. A flip-flop (sometimes called a _____) in logic gate diagrams is a design that can be used to store a single bit of information, either a one or a zero
2. A flip-flop is a basic _______ which can store one bit and _____ it between 0 and 1.
3. The first electronic flip-flop was invented in 1918 by the British physicists William Eccles and F. W. Jordan. Fill in the blanks.
4. Flip flops have two inputs - a _________ input (often labelled as D) and a ______ signal.
5. The clock signal in a flip flop is provided by another basic circuit and it is responsible for ____________________at regular intervals or pulses.
6. Internal regular pulses or heart beats are crucial to hardware. In flip flops, the clock is used to _______________ the changing of state of the flip flop circuit.
7. A D type flip flop circuit is a positive edge triggered circuit which means that the output can only be changed from 1 to 0 or 0 to 1 when _____________________
8. Look at the following diagram. Which of the following statements is correct?
9. The D type flip-flop has a maximum of three inputs and only a single output
10. Flip-flops can be either simple (transparent or asynchronous) or clocked (synchronous). The simple ones are commonly described as latches _________________
11. D flip flops are popular with digital electronics. They are commonly used for which of the following:
12. In a D flip flop, the output can be only changed at the rising clock edge (start of cycle). If the input changes at other times, ____________
13. In a D flip flop, the change of state of the output is dependent on the
14. The output Q always takes on whatever state the Data signal D is in, but only when the clock is on a_______________
15. In the following diagram, fill in the blanks for 'A' and 'B'. Note the clock input.
16. You could picture a 'clock' in this situation as a ______________________: each one has a rising and a falling edge.
17. SR Latch stands for set reset latch and can be thought of as a ________________
18. The SR latch can be built using:
19. In the SR latch below, fill in the blanks indicated by the red box. What is output?
20. One main disadvantage of the basic SR NAND Gate Bistable circuit is that the indeterminate input condition of SET = “0” and RESET = “0” is forbidden.
21. The uses of D-type flip flops include the creation of register memory as well as static RAM.
22. The D-type flip flop are constructed from a gated SR flip-flop with an inverter added between the S and the R inputs to allow for _______________
23. A D-type flip flop could be used as a “Frequency Divider” to produce a “divide-by-2” counter circuit, that is, the output has __________________
24. The difference between a D-type latch and a D-type flip-flop is that a latch does not have a clock signal to change state whereas a flip-flop always does
25. Analyse the following Master-Slave D Flip Flop Circuit. Which of the following statements are true?
26. This flip flop has only one input labelled D, and a clock. The addition of the NOT gate ensures that the inputs to the clocked S-R flip flop ___________
27. Read the excerpt below and fill in the blanks
28. In a D type flip-flop,changes to the output occur immediately when a change to the inputs occurs
29. Read the following excerpt that explains how the given problem is resolved. Fill in the blanks
30. Read the following excerpt about the reality (or not, as may be the case) of the delay factor involved. True or False?