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11 - D type flip flops

1. A flip-flop (sometimes called a _____) in logic gate diagrams is a design that can be used to store a single bit of information, either a one or a zero

In electronics, a flip-flop or _____ is a circuit 
that has two stable states and can be used to 
store state information

circuiter

bit

latch

sequence

2. A flip-flop is a basic _______ which can store one bit and _____ it between 0 and 1.

circuit / flip

bit sequence / flip

AND gate / flip

NAND gate / flop

3. The first electronic flip-flop was invented in 1918 by the British physicists William Eccles and F. W. Jordan. Fill in the blanks.

It was initially called the Eccles–Jordan trigger 
circuit and consisted of two active elements (vacuum tubes) 
The design was used in the 1943 British ______________
codebreaking computer

Colossus

Apple Mac

Enollum

BRAINAC

4. Flip flops have two inputs - a _________ input (often labelled as D) and a ______ signal.

clock / CPU

control / clock

control / heart

wave / digital

5. The clock signal in a flip flop is provided by another basic circuit and it is responsible for ____________________at regular intervals or pulses.

constantly changing states from 1 to 0 and 0 to 1

reversing every state to ensure an output of a 0

inverting the states ensuring an output of a 1

changing the states from 1 to 0 but not from 0 to 1

6. Internal regular pulses or heart beats are crucial to hardware. In flip flops, the clock is used to _______________ the changing of state of the flip flop circuit.

stabilise

invert

synchronise

disturb

7. A D type flip flop circuit is a positive edge triggered circuit which means that the output can only be changed from 1 to 0 or 0 to 1 when _____________________

the clock pulse is at a 'falling' edge or negative edge

the clock pulse is inverted

the clock pulse is at a 'rising' or positive edge

the clock pulse is temporarily stopped

8. Look at the following diagram. Which of the following statements is correct?

A is the falling edge and B is is the rising edge

A and B are both falling edges

A and B are both rising edges

A is the rising edge and B is the falling edge

9. The D type flip-flop has a maximum of three inputs and only a single output

TRUE

FALSE

10. Flip-flops can be either simple (transparent or asynchronous) or clocked (synchronous). The simple ones are commonly described as latches _________________

while the complex ones are described as clocks

while the clocked ones are described as the 'D' bits

while the clocked ones are described as clock-o-naughts

while the clocked ones are described as flip-flops

11. D flip flops are popular with digital electronics. They are commonly used for which of the following:

counters

shift-registers

All of the options mentioned here are valid

input synchronisation

12. In a D flip flop, the output can be only changed at the rising clock edge (start of cycle). If the input changes at other times, ____________

the output will be unaffected

the output will drop down to a 0

the output will also be affected

the output will be automatically changed to a 1

13. In a D flip flop, the change of state of the output is dependent on the

Note: D for Data

input as well as the output which is input back into the system again

rising edge of the clock

first input only

inverted input

14. The output Q always takes on whatever state the Data signal D is in, but only when the clock is on a_______________

a rising edge

curved edge

non edge

falling edge

15. In the following diagram, fill in the blanks for 'A' and 'B'. Note the clock input.

A is 0 and B is 1

A and B are both 1

A and B are both 0

A is 1 and B is 0

16. You could picture a 'clock' in this situation as a ______________________: each one has a rising and a falling edge.

continuous series of digital pulses

eight bit stream of waves

pair of digital pulses

stream of 'And' gates

17. SR Latch stands for set reset latch and can be thought of as a ________________

4 bit memory

1 bit memory

3 bit memory

2 bit memory

18. The SR latch can be built using:

AND gates only

OR gates only

NOR or NAND gates

NOR gates only

19. In the SR latch below, fill in the blanks indicated by the red box. What is output?

1 and 0 at the same time (like a quibit)

ERROR

20. One main disadvantage of the basic SR NAND Gate Bistable circuit is that the indeterminate input condition of SET = “0” and RESET = “0” is forbidden.

Note: The circuit can be changed such that an
inverter can be connected between the “SET” 
and the “RESET” inputs to produce another type 
of flip flop circuit known as a Data Latch, 
Delay flip flop, D-type Bistable, D-type Flip 
Flop or just simply a D Flip Flop as it is 
more generally called.
This resolves the disadvantage mentioned.

FALSE

TRUE

21. The uses of D-type flip flops include the creation of register memory as well as static RAM.

FALSE

TRUE

22. The D-type flip flop are constructed from a gated SR flip-flop with an inverter added between the S and the R inputs to allow for _______________

a single D (data) input

a duplicate D (data) output

a falling edge clock pulse output (e.g. -1)

two D outputs of 0 or 1

23. A D-type flip flop could be used as a “Frequency Divider” to produce a “divide-by-2” counter circuit, that is, the output has __________________

double the frequency of the clock pulses

duplicate the frequency as symbolised by 2D

a digitial frequency of '1'

half the frequency of the clock pulses

24. The difference between a D-type latch and a D-type flip-flop is that a latch does not have a clock signal to change state whereas a flip-flop always does

FALSE

TRUE

25. Analyse the following Master-Slave D Flip Flop Circuit. Which of the following statements are true?

Master-Slave D Flip Flop Circuit
=================================
1. There will always be one flip-flop “ON” 
and the other “OFF” but never both the master 
and slave “ON” at the same time.

2. The output Q acquires the value of D, only
when one complete pulse, ie, 0-1-0 is applied 
to the clock input.

3. Master-Slave D-type flip flops” can be 
constructed by the cascading together of two 
latches with exactly the same (not opposite) 
clock phases

1 and 2 only

1, 2 and 3 are all correct

1 only

2 and 3 only

26. This flip flop has only one input labelled D, and a clock. The addition of the NOT gate ensures that the inputs to the clocked S-R flip flop ___________

will be always set to 1

will always be the same

will always be the opposite of the output Q

can now never be the same.

27. Read the excerpt below and fill in the blanks

To RESET the D-type flip-flop it is simply a case 
of setting the D input to Logic 0, and then setting 
the clock to Logic 1. The output Q will then become 
a Logic 0, and   will be a Logic 1.

A simple way of remembering this is that the Logic 
state of the D input is _________________________
_________________________________________________

transferred to the Q output when the clock is low

low when the clock output is low

high when the Q output of the clock is either high or low

transferred to the Q output when the clock is high.

28. In a D type flip-flop,changes to the output occur immediately when a change to the inputs occurs

FALSE

TRUE

29. Read the following excerpt that explains how the given problem is resolved. Fill in the blanks

If you are reading information from a memory i.e. where 16-bits of information have to be taken at the same time, each data line from the memory will take fractionally different lengths of time to settle at logic 0 or 1, so it important that time is allowed for the data to settle before it is ‘read’ and decisions made based on its content.

This is achieved by the introduction of a _____ line, 
a single digital input which when it is at Logic 1, causes a change in the output, if such a change is required due to the logic state of the inputs.

clock

sequential

binary

wave-based

30. Read the following excerpt about the reality (or not, as may be the case) of the delay factor involved. True or False?

It is often assumed in logic gates that changes occur at the output of the logic gates at the same instant that the input changes. 

The reality is not so. There is a very small delay between a change at the input and the output responding to that change which is called the propagation delay and this occurs for all logic gates.

TRUE

FALSE

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