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1. An adder is a digital logic circuit in electronics that implements addition of numbers
```In many computers and other types of processors,
operations and table indices in the ALU and also
in other parts of the processors.```

TRUE

FALSE

2. With the help of half adder, we can design circuits that are capable of performing _____________ with the help of logic gates.

subtraction

complex recursion

3. From analysis of the below, it is clear that this 1-bit adder can be easily implemented with the help of XOR/EXOR Gate for the output ‘SUM’ and an ____ Gate for the carry.
```0+0 = 00

0+1 = 01

1+0 = 01

1+1 = 10

Here the output ‘1’of ‘10’ becomes the carry-out.
The result is shown in a truth-table below. ‘SUM’
is the normal output and ‘CARRY’ is the carry-out.

INPUTS                       OUTPUTS
============================================

A              B              SUM           CARRY
-------------------------------------------------

0              0              0              0

0              1              1              0

1              0              1              0

1              1              0              1```

OR

NOT

AND

NOR

4. In the half adder circuit below, what are the values for SUM and CARRY?

SUM = 0; CARRY = 1

SUM and CARRY = 1

SUM = 1; CARRY = 0

SUM and CARRY = 0

5. Half adders allow for complex addition, i.e cases when you have to add two 8-bit bytes together.

TRUE

FALSE

6. A half adder circuit can add _______________and produce a digit bit (Q) and a carry bit.

up to 8 billion bit numbers

clock signals together with a single bit number

two single bit numbers

only 1s in a binary number

7. A half adder specialises in dealing effectively with an incoming carry bit.

FALSE

TRUE

8. One of the differences between a half adder and a full adder is that the full adder has three inputs and two outputs

FALSE

TRUE

9. The half adder is a combination circuit of____________________ circuits. Its purpose, as the name suggests, is to add numbers

AND and NAND

XOR and AND

OR and NOT

OR and XOR

10. It is possible, as shown in the diagram below, to construct a half adder using only NAND gates.

TRUE

FALSE

11. The half adder has two outputs, sum (S) and carry (C). The carry signal represents an _______into the next digit of a multi-digit addition

oddity

overflow

exception

OR gate

12. In a half adder, the value of the sum is 2C + C + S.

TRUE

FALSE

13. With the addition of an _____to combine their carry outputs, two half adders can be combined to make a full adder

OR gate

AND gate

NOR gate

NOT gate

14. Can you spot the error in the following truth table for a half adder circuit?
```Inputs	Outputs
A	B	C	S
-------------------------
0	0	1	0
1	0	0	1
0	1	0	1
1	1	1	0```

It is not possible to create a truth table for a half adder as it is not complete

For the input A,B = 0,0, the 'Carry' output should be 0

For the input A,B = 1,0, the SUM should be 0.

There are no errors

15. What is the following diagram showing?

Logic diagram for a half adder

Logic diagram for two half adders connected to an 'AND' gate

Logic diagram for several XOR, AND and OR gates - an adder has not been created in this example

Logic diagram for a full adder